(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to reduce contact node resistance thereby improving data retention for logic-based DRAM devices.
(2) Description of the Prior Art
For the mass production of semiconductor integrated devices many devices are typically concurrently produced by the simultaneous creation of device features in silicon substrates. In this creation of device features, materials having vastly different characteristics and electrical properties are used to provide the different functions for each of the device features. Categories of materials that are used for this purpose are materials that are electrically conducting, non-conducting or semiconducting. The substrate on Which these devices are created is most commonly of silicon, the silicon can be either of single crystalline structure or of poly crystalline structure, both of these crystalline structures can be made to become electrically conducting by doping the silicon with impurities. These impurities can be of different electrical types and can contain fewer electrons ("holes") in their molecular structure than silicon or the impurities can contain more electrons in their molecular structure than silicon. The former (for instance boron or indium) creates p-type silicon after the silicon is doped with this impurity; the latter (for instance phosphorous or arsenic) creates n-type silicon.
The functions that are performed by data processing systems can broadly be divided into the function of manipulating data, the logic function, and the function of retaining or storing data, the memory function. While these functions can at times be encountered on one and the same semiconductor chip, these function are in many cases provided by chips that are specifically dedicated to either one or to the other function.
The Dynamic Random Access Memory (DRAM) is typically used for the function of data storage and consists of arrays of memory cells that form two basic functions, that is the field effect transistor that serves as a charge transfer transistor and a capacitor. The field effect transistor (a source region, a drain region and a gate electrode) serves the function of providing access to the capacitor whereby the capacitor serves the function of data retention or storage. Binary data is stored as electrical charge on the capacitor in the individual DRAM memory cells. Contacts to the surrounding circuits are provided for the DRAM memory cell. DRAM memory is so named because its cells can retain information only for a limited period of time before they must be read and refreshed at periodic intervals. In a typical DRAM construction, one side of the transistor i s connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connect points that form the bit and word line. The other side of the capacitor is connected to a reference voltage.
The processing technology in the manufacturing of Dynamic Random Access Memory (DRAM) has, during the last several decades, migrated from 0.8 um 4M memories to 0.25 um 256M memories with a continuing decrease in memory cell size and concurrent increase in memory capacity. It is expected that in the near future the number of memory cells that can be fabricated on one chip will increase to 1 Gigabit. This scaling down in memory cell capacity puts increased emphasis on the dielectric isolation between the DRAM cells since this dielectric isolation im pact s data retention capability. Semiconductor manufacturing processing efficiencies are enhanced by reductions in device feature size, in t his effort the capacitor of the DRAM device is usually the largest element of the Integrated Circuit chip. For bit densities of up to one megabit, planar-type storage capacitors are used. However, as storage densities increase, the amount of charges needed for a sufficient noise margin remains fixed. Therefore, in order to increase the specific capacitance, two different routes have been taken. The first is to store charges vertically in a trench. The second solution, which allows the cell to shrink in size without losing storage capacity, is to stack the capacitor on top of the access transistor. It is apparent from this that, as the memory density increases; the capacitor structure becomes more intricate and grows in the vertical direction.
DRAM storage cell capacity can be increased by making the capacitor dielectric thinner, by using a dielectric with a larger dielectric constant or by increasing the area of the capacitor. The first two options are not currently available since capacitor dielectrics thinner than those now being used in DRAM cells will suffer leakage due to an electron tunneling effect. Dielectrics with significantly larger dielectric constants than that of SiO.sub.2 have not yet been accepted for DRAM application.
It must also be noted that, since the 256-kbit DRAM generation, bi-layer films (consisting of both silicon nitride and SiO.sub.2) have been used as the capacitor dielectric to increase cell capacitance. The higher dielectric constant of Si.sub.3 Ni.sub.4 (twice as large as that of SiO.sub.2) is responsible for this increase.
The approach of storing charges vertically in a trench results in stacking the storage capacitor on top of the access transistor. The lower electrode of the stacked capacitor (STC) is in contact with the drain of the access transistor whereby the bit line runs over the top of the stacked capacitor. For STC cells to be made feasible for larger capacity DRAM's, an insulator with a larger dielectric constant than that of SiO.sub.2 must be used.
The invention addresses the formation of the plugs that make contact with the capacitor and the bit or word lines in the highlighted construction of a DRAM device. FIGS. 2 through 4 shows a number of Prior Art methods that are applied for this process.
FIG. 2 shows a cross section of the present process of the formation of plug 43. FIG. 2a shows how the current process creates the lightly doped region 40 of polysilicon and the High Temperature Film (HTF) 41 for the formation of plug 43, layers 42 and 44 can represent an adjacent gate electrode and an underlying stress relieve layer respectively. The structure shown in FIG. 2 has been created on the surface of a silicon substrate 47. The HTF region 41 is heavily doped and formed at a temperature of about 750 degrees C. FIG. 2b shows the poly plug after polishing. FIG. 2c shows the creation of a second plug on top of the first plug. The layer of lightly doped poly 40 has been extended with a second layer 43 of lightly doped poly over which the capacitor structure 45 has been created. The top surface of the HTF region 41 has formed a layer of native oxide that typically forms on heavily doped poly, this layer of oxide increases the contact resistance between the two layers 40/41 and 43 in the region 46. This increase in contact resistance degrades device performance.
FIG. 3 shows another current approach in forming contact plugs. In using lightly doped poly, the thermal budget for the process can be reduced. FIG. 3 shows a process where lightly doped poly has been used. FIG. 3a shows the typical plug 46 formation, FIG. 3b shows the plug after CMP of the top surface of the plug, FIG. 3c shows the plug after the plug 46 has been extended with a second layer 48 of lightly doped poly and the capacitor 50 has been created in contact with the second layer 48 of poly. The reduced thermal budget that can be used for this process has however increased the node contact resistance (between layers 46 and 48) which again degrades device performance.
FIG. 4 shows yet another approach that can be used to make contact plugs. FIG. 4a shows how the plug 52, made using lightly doped poly, is implanted (51) with an n-type dopant, region 53 in the geometric center of the plug indicates the region where the dopant concentration is heaviest. FIG. 4b shows the plug after CMP, FIG. 4c shows the plug after the plug 52 has been extended with a second layer 54 of poly and connected to capacitor 56. The dopant distribution 53 in the lower section of the plug is uneven with low concentration of dopant at the interface between the plug and the underlying silicon 47. The dopant also has a low concentration at the top region 55 of the lower section of the plug where the first layer of the plug intersects with the second, lightly doped, second layer 54. This results in an increase of the contact resistance of this portion of the overall plug. In addition, the implant of the dopant into the section 52 (FIG. 4a) has caused molecular lattice network damage to section 52 which further increases the contact resistance at the intersect between 54 and 55. These effects degrade device performance.
The invention address a method for forming contact plugs whereby device performance is not degraded. Typically lightly doped poly is used for the formation of the highlighted DRAM device plugs. It is however the tendency in the formation of logic imbedded DRAM devices to reduce the thermal budget for the process, this results in increased contact resistance. Increased contact resistance results in low charge efficiency making data retention more difficult to achieve.